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electrical specifications subject to change ltc2205/ltc2204 1 22054p features descriptio u applicatio s u typical applicatio u 16-bit, 65msps/40 msps adcs the ltc ? 2205/ltc2204 are sampling 16-bit a/d converters designed for digitizing high frequency, wide dynamic range signals up to input frequencies of 700mhz. the input range of the adc can be optimized with the pga front end. the ltc2205/ltc2204 are perfect for demanding com- munications applications, with ac performance that in- cludes 78db snr and 100db spurious free dynamic range (sfdr). ultralow jitter of 120fs rms allows undersampling of high input frequencies with excellent noise performance. maximum dc specs include 4lsb inl, 1lsb dnl (no missing codes) over temperature. a separate output power supply allows the cmos output swing to range from 0.5v to 3.3v. the enc + and enc C inputs may be driven differentially or single-ended with a sine wave, pecl, lvds, ttl or cmos inputs. an optional clock duty cycle stabilizer al- lows high performance at full speed with a wide range of clock duty cycle. telecommunications receivers cellular base stations spectrum analysis imaging systems ate sample rate: 65msps/40msps 79db snr and 100db sfdr (2.25v range) sfdr >83db at 170mhz (1.5v p-p input range) pga front end (2.25v p-p or 1.5v p-p input range) 700mhz full power bandwidth s/h optional internal dither optional data output randomizer single 3.3v supply power dissipation: 530mw/470mw optional clock duty cycle stabilizer out-of-range indicator pin compatible family 105msps: ltc2207 (16-bit) 80msps: ltc2206 (16-bit) 65msps: ltc2205 (16-bit), 40msps: ltc2204 (16-bit) 48-pin qfn package ? + s/h amp correction logic and shift register output drivers 16-bit pipelined adc core internal adc reference generator 1.25v common mode bias voltage clock/duty cycle control d15 d0 enc pga shdn dith mode oe rand enc v cm analog input 22076 ta01 0.5v to 3.3v 3.3v 3.3v sense ognd ov dd 2.2 f 1 f 1 f 1 f 1 f v dd gnd adc control inputs ain + ain ? of clkout , ltc and lt are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
ltc2205/ltc2204 2 22054p absolute axi u rati gs w ww u for atio package/order i uu w co verter characteristics u parameter conditions min typ max units resolution (no missing codes) 16 bits integral linearity error differential analog input (note 5) 0.7 4 lsb differential linearity error differential analog input 0.3 1 lsb offset error (note 6) 1 5 mv offset drift 10 v/ c gain error external reference 0.2 0.5 %fs full-scale drift internal reference 30 ppm/c external reference 10 ppm/c transition noise 2.5 lsb rms supply voltage (v dd ) ................................... C0.3v to 4v digital output ground voltage (ognd) ........ C0.3v to 1v analog input voltage (note 3) ......C0.3v to (v dd + 0.3v) digital input voltage .....................C0.3v to (v dd + 0.3v) digital output voltage ................ C0.3v to (ov dd + 0.3v) power dissipation ............................................ 2000mw operating temperature range ltc2205c/LTC2204C ............................... 0c to 70c ltc2205i/ltc2204i ............................. C40c to 85c storage temperature range .................. C65c to 150c digital output supply voltage (ov dd ) .......... C0.3v to 4v ov dd = v dd (notes 1 and 2) the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) top view uk package 48-lead (7mm 7mm) plastic qfn sense 1 v cm 2 v dd 3 v dd 4 gnd 5 ain + 6 ain ? 7 gnd 8 enc + 9 enc ? 10 gnd 11 v dd 12 36 ovp 35 d11 34 d10 33 d9 32 d8 31 ognd 30 clkout + 29 clkout ? 28 d7 27 d6 26 d5 25 ovp 48 gnd 47 pga 46 rand 45 mode 44 oe 43 of 42 d15 41 d14 40 d13 39 d12 38 ognd 37 ovp v dd 13 v dd 14 gnd 15 shdn 16 dith 17 d0 18 d1 19 d2 20 d3 21 d4 22 ognd 23 ovp 24 49 exposed pad is gnd (pin 49) must be soldered to pcb board t jmax = 125c, ja = 29c/w order part number uk part marking* ltc2205c LTC2204C ltc2205i ltc2204i xxxxx xxxxx order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container.
ltc2205/ltc2204 3 22054p a alog i pu t uu the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) dy a ic accuracy u w the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. a in = C 1dbfs. (note 4) symbol parameter conditions min typ max units v in analog input range (a in + C a in C ) 3.135v v dd 3.465v 1.5 to 2.25 v p-p v in, cm analog input common mode differential input (note 7) 1 1.25 1.5 v i in analog input leakage current 0v a in + , a in C v dd C1 1 a i sense sense input leakage current 0v sense v dd C1 1 a i mode mode pin pull-down current to gnd 10 a c in analog input capacitance sample mode enc + < enc C 6 pf hold mode enc + > enc C 1.2 t ap sample-and-hold C0.7 ns acquisition delay time t jitter sample-and-hold 120 fs rms acquisition delay time jitter cmrr analog input 1v < (a in + = a in C ) <1.5v 80 db common mode rejection ratio bw-3db full power bandwidth 700 mhz symbol parameter conditions min ltc2204 typ max min ltc2205 typ max units snr signal-to-noise ratio 5mhz input (2.25v range, pga = 0) 5mhz input (1.5v range, pga = 1) 79.0 76.4 79.0 76.4 dbfs dbfs 25mhz input (2.25v range, pga = 0) 25mhz input (1.5v range, pga = 1) tbd 77.9 75.7 tbd 77.9 75.7 dbfs dbfs 70mhz input (2.25v range, pga = 0) 70mhz input (1.5v range, pga = 1) 72.6 71.7 72.6 71.7 dbfs dbfs 140mhz input (2.25v range, pga = 0) 140mhz input (1.5v range, pga = 1) 67.3 67.0 67.3 67.0 dbfs dbfs 170mhz input (2.25v range, pga = 0) 170mhz input (1.5v range, pga = 1) tbd 65.4 65.2 tbd 65.4 65.2 dbfs dbfs sfdr spurious free dynamic range 2 nd or 3 rd harmonic 5mhz input (2.25v range, pga = 0) 5mhz input (1.5v range, pga = 1) 100 100 100 100 db db 25mhz input (2.25v range, pga = 0) 25mhz input (1.5v range, pga = 1) tbd 90 90 tbd 90 90 db db 70mhz input (2.25v range, pga = 0) 70mhz input (1.5v range, pga = 1) 90 90 90 90 db db 140mhz input (2.25v range, pga = 0) 140mhz input (1.5v range, pga = 1) 82 85 82 85 db db 170mhz input (2.25v range, pga = 0) 170mhz input (1.5v range, pga = 1) tbd 82 84 tbd 82 84 db db sfdr spurious free dynamic range 4 th harmonic or higher 5mhz input (2.25v range, pga = 0) 5mhz input (1.5v range, pga = 1) 105 105 105 105 db db 25mhz input (2.25v range, pga = 0) 25mhz input (1.5v range, pga = 1) tbd 98 98 tbd 98 98 db db 70mhz input (2.25v range, pga = 0) 70mhz input (1.5v range, pga = 1) 100 100 100 100 db db 140mhz input (2.25v range, pga = 0) 140mhz input (1.5v range, pga = 1) 97 97 97 97 db db 170mhz input (2.25v range, pga = 0) 170mhz input (1.5v range, pga = 1) tbd 95 95 tbd 95 95 db db
ltc2205/ltc2204 4 22054p co o ode bias characteristics u uu u uu u parameter conditions min typ max units v cm output voltage i out = 0 1.15 1.25 1.35 v v cm output tempco i out = 0 100 ppm/c v cm line regulation 3.135v v dd 3.465v 1 mv/ v v cm output resistance 1ma | i out | 1ma 2 the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. a in = C1dbfs unless otherwise noted. (note 4) the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) symbol parameter conditions min ltc2204 typ max min ltc2205 typ max units s/(n+d) signal-to-noise plus distortion ratio 5mhz input (2.25v range, pga = 0) 5mhz input (1.5v range, pga = 1) 79.0 76.5 79.0 76.5 dbfs dbfs 25mhz input (2.25v range, pga = 0) 25mhz input (1.5v range, pga = 1) tbd 77.5 75.5 tbd 77.5 75.5 dbfs dbfs 70mhz input (2.25v range, pga = 0) 70mhz input (1.5v range, pga = 1) 72.3 71.6 72.3 71.6 dbfs dbfs 140mhz input (2.25v range, pga = 0) 140mhz input (1.5v range, pga = 1) 67.0 66.9 67.0 66.9 dbfs dbfs 170mhz input (2.25v range, pga = 0) 170mhz input (1.5v range, pga = 1) tbd 65.3 65.1 tbd 65.3 65.1 dbfs dbfs sfdr spurious free dynamic range at C25dbfs dither off 5mhz input (2.25v range, pga = 0) 5mhz input (1.5v range, pga = 1) 105 105 105 105 dbfs dbfs 25mhz input (2.25v range, pga = 0) 25mhz input (1.5v range, pga = 1) tbd 105 105 tbd 105 105 dbfs dbfs 70mhz input (2.25v range, pga = 0) 70mhz input (1.5v range, pga = 1) 105 105 105 105 dbfs dbfs 140mhz input (2.25v range, pga = 0) 140mhz input (1.5v range, pga = 1) 100 100 100 100 dbfs dbfs 170mhz input (2.25v range, pga = 0) 170mhz input (1.5v range, pga = 1) tbd 100 100 tbd 100 100 dbfs dbfs sfdr spurious free dynamic range at C25dbfs dither off 5mhz input (2.25v range, pga = 0) 5mhz input (1.5v range, pga = 1) 115 115 115 115 dbfs dbfs 25mhz input (2.25v range, pga = 0) 25mhz input (1.5v range, pga = 1) tbd 115 115 tbd 115 115 dbfs dbfs 70mhz input (2.25v range, pga = 0) 70mhz input (1.5v range, pga = 1) 115 115 115 115 dbfs dbfs 140mhz input (2.25v range, pga = 0) 140mhz input (1.5v range, pga = 1) 115 115 115 115 dbfs dbfs 170mhz input (2.25v range, pga = 0) 170mhz input (1.5v range, pga = 1) tbd 105 105 tbd 105 105 dbfs dbfs dy a ic accuracy u w
ltc2205/ltc2204 5 22054p the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) digital i puts a d digital output s uu symbol parameter conditions min typ max units encode inputs (enc + , enc C ) v id differential input voltage 0.2 v v icm common mode input voltage internally set 1.6 v externally set (note 7) 1.2 v dd r in input resistance (see figure 2) 6 k c in input capacitance (note 7) 3 pf logic inputs (dith, pga, shdn, rand) v ih high level input voltage v dd = 3.3v 2 v v il low level input voltage v dd = 3.3v 0.8 v i in digital input current v in = 0v to v dd 10 a c in digital input capacitance (note 7) 1.5 pf logic outputs ov dd = 3.3v v oh high level output voltage v dd = 3.3v i o = C10a 3.299 v i o = C200a 3.0 3.29 v v ol low level output voltage v dd = 3.3v i o = 160a 0.01 v i o = 1.6ma 0.10 0.4 v i source output source current v out = 0v C50 ma i sink output sink current v out = 3.3v 50 ma ov dd = 2.5v v oh high level output voltage v dd = 3.3v i o = C200a 2.49 v v ol low level output voltage v dd = 3.3v i o = 1.60ma 0.1 v ov dd = 1.8v v oh high level output voltage v dd = 3.3v i o = C200a 1.79 v v ol low level output voltage v dd = 3.3v i o = 1.60ma 0.1 v power require e ts w u the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. a in = C1dbfs. (note 9) symbol parameter conditions min ltc2204 typ max min ltc2205 typ max units v dd analog supply voltage 3.135 3.3 3.465 3.315 3.3 3.465 v p shdn shutdown power shdn = v dd 22mw ov dd output supply voltage 0.5v 3.6 0.5v 3.3 3.6 v i vdd analog supply current 141 160 ma p dis power dissipation 470 580 mw
ltc2205/ltc2204 6 22054p ti i g diagra w u w t h t d t c t l n ? 7 n ? 6 n ? 5 n ? 4 n ? 3 analog input enc ? enc + clkout ? clkout + d0-d15, of 22054 td01 t ap n + 1 n + 2 n + 4 n + 3 n note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd, with gnd and ognd shorted (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: v dd = 3.3v, f sample = 65mhz (ltc2205), 40mhz (ltc2204) differential enc + /enc C = 2v p-p sine wave with 1.6v common mode, input range = 2.25v p-p with differential drive (pga = 0), unless otherwise speci? ed. note 5: integral nonlinearity is de? ned as the deviation of a code from a best ? t straight line to the transfer curve. the deviation is measured from the center of the quantization band. note 6: offset error is the offset voltage measured from C1/2lsb when the output code ? ickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 in 2s complement output mode. note 7: guaranteed by design, not subject to test. note 8: recommended operating conditions. ti i g characteristic s w u the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) symbol parameter conditions min ltc2204 typ max min ltc2205 typ max units f s sampling frequency 1 40 1 65 mhz t l enc low time duty cycles stabilizer off duty cycles stabilizer on 12.5 12.5 500 500 7.69 7.69 500 500 ns ns t h enc high time duty cycles stabilizer off duty cycles stabilizer on 12.5 12.5 500 500 7.69 7.69 500 500 ns ns t ap sample-and-hold aperture delay 00ns t d enc to data delay (note 7) 1.3 2.1 3.5 1.3 2.1 3.5 ns t c enc to clkout delay (note 7) 1.3 2.1 3.5 1.3 2.1 3.5 ns t skew data to clkout skew (t c -t p ) (note 7) C1.6 0 0.6 C1.6 0 0.6 ns t oe data access time bus relinquish time cl = 5pf (note 7) (note 7) 5 5 15 15 5 5 15 15 ns ns pipeline latency 7 7 cycles
ltc2205/ltc2204 7 22054p typical perfor uw ce characteristics a ltc2205: inl (integral non- linearity) vs code ltc2205: dnl (differential non- linearity) vs code ltc2205: grounded input histogram ltc2205: 32k point fft, f in = 5.1mhz, C1db, 65msps, pga = 0 ltc2205: 32k point fft, f in = 5.1mhz, C1db, 65msps, pga = 1 ltc2205: 32k point fft, f in = 5.1mhz, C40db, 65msps, pga = 0, dith = 0 ltc2205: 32k point fft, f in = 5.1mhz, C40db, 65msps, pga = 0, dith = 1 ltc2205: 32k point fft, f in = 5.1mhz, C40db, 65msps, pga = 1, dith = 0 ltc2205: 32k point fft, f in = 5.1mhz, C40db, 65msps, pga = 1, dith = 1 code 0 inl (lsb) 0 1.0 65536 22054 g01 ?1.0 ?2.0 16384 32768 49152 8192 24576 40960 57344 2.0 ?0.5 0.5 ?1.5 1.5 code 0 dnl (lsb) 0 0.50 65536 22054 g02 ?0.50 ?1.00 16384 32768 49152 8192 24576 40960 57344 1.00 ?0.25 0.25 ?0.75 0.75 code from mid-scale ?10 count 100,000 120,000 10 22054 g03 60,000 0 ?8 ?6 ?2 ?4 02 6 48 160,000 140,000 80,000 40,000 20,000 frequency (mhz) 0 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 15 25 22054 g04 510 20 30 amplitude (dbfs) frequency (mhz) 0 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 15 25 22054 g05 510 20 30 amplitude (dbfs) frequency (mhz) 0 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 15 25 22054 g06 510 20 30 amplitude (dbfs) frequency (mhz) 0 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 15 25 22054 g07 510 20 30 amplitude (dbfs) frequency (mhz) 0 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 15 25 22054 g08 510 20 30 amplitude (dbfs) frequency (mhz) 0 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 15 25 22054 g09 510 20 30 amplitude (dbfs)
ltc2205/ltc2204 8 22054p typical perfor a ce characteristics uw ltc2205: gain error drift with internal reference vs temp ltc2205: gain drift with external reference vs temp ltc2205: 32768 point fft, f in = 70.1mhz, C20db, pga = 0, dith = 0, rand = 0 ltc2205: 32768 point fft, f in = 140.1mhz, C1db, pga = 1, dith = 0, rand = 0 ltc2205: 32768 point fft, f in = 140.1mhz, C10db, pga = 1, dith = 0, rand = 0 ltc2205: 32768 point fft, f in = 140.1mhz, C20db, pga = 1, dith = 0, rand = 0 ltc2205: 32768 point fft, f in = 170.1mhz, C1db, pga = 1, dith = 0, rand = 0 ltc2205: 32768 point fft, f in = 170.1mhz, C10db, pga = 1, dith = 0, rand = 0 ltc2205: 32768 point fft, f in = 170.1mhz, C20db, pga = 1, dith = 0, rand = 0 temperature ( c) ?60 drift (mv) ?3 ?1 100 22054 g10 ?5 ?7 ?20 20 60 ?40 0 40 80 1 ?4 ?2 ?6 0 temperature ( c) ?60 ?1.2 gain drift (mv) ?1.0 ?0.6 ?0.4 ?0.2 0.8 0.2 ?20 20 40 22054 g11 ?0.8 0.4 0.6 0 ?40 0 60 80 100
ltc2205/ltc2204 9 22054p typical perfor a ce characteristics uw ltc2205: 32768 point fft, f in = 350.1mhz, C1db, pga = 1, dith = 0, rand = 0 ltc2205: 32768 point fft, f in = 350.1mhz, C10db, pga = 1, dith = 0, rand = 0 ltc2205: 32768 point fft, f in = 350.1mhz, C20db, pga = 1, dith = 0, rand = 0 ltc2205: 32768 point 2-tone fft, f in = 30.1mhz, 31.1mhz, C7db, pga = 0, dith = 0, rand = 0 ltc2205: 32768 point 2-tone fft, f in = 70.1mhz, 71.1mhz, C7db, pga = 0, dith = 0, rand = 0 ltc2205: 32768 point 2-tone fft, f in = 250.1mhz, 251.1mhz, C7db, pga = 1, dith = 0, rand = 0 ltc2205: sfdr vs input level, f in = 5.1mhz, pga = 0, dith = 0, rand = 0 ltc2205: sfdr vs input level, f in = 5.1mhz, pga = 0, dith = 1, rand = 1 ltc2205: sfdr vs input level, f in = 30.1mhz, pga = 0, dith = 0, rand = 0
ltc2205/ltc2204 10 22054p typical perfor a ce characteristics uw ltc2205: sfdr vs input level, f in = 30.1mhz, pga = 0, dith = 1, rand = 1 ltc2205: sfdr vs input level, f in = 70.1mhz, pga = 0, dith = 0, rand = 0 ltc2205: sfdr vs input level, f in = 70.1mhz, pga = 0, dith = 1, rand = 1 ltc2205: sfdr vs input level, f in = 140.1mhz, pga = 0, dith = 0, rand = 0 ltc2205: sfdr vs input level, f in = 140.1mhz, pga = 0, dith = 1, rand = 1 ltc2205: sfdr vs input level, f in = 170.1mhz, pga = 0, dith = 0, rand = 0 ltc2205: sfdr vs input level, f in = 170.1mhz, pga = 0, dith = 1, rand = 1 ltc2205: sfdr vs input level, f in = 350.1mhz, pga = 0, dith = 0, rand = 0 ltc2205: sfdr vs input level, f in = 350.1mhz, pga = 0, dith = 1, rand = 1
ltc2205/ltc2204 11 22054p ltc2205: snr vs input frequency, pga = 0, dith = 0, rand = 0 ltc2205: snr vs input frequency, pga = 1, dith = 0, rand = 0 ltc2205: sfdr (hd2 and hd3) vs input frequency, pga = 0, dith = 0, rand = 0 ltc2205: sfdr (hd2 and hd3) vs input frequency, pga = 1, dith = 0, rand = 0 ltc2205: sfdr (hd4 and higher) vs input frequency, pga = 0, dith = 0, rand = 0 ltc2205: sfdr (hd4 and higher) vs input frequency, pga = 1, dith = 0, rand = 0 ltc2205: sfdr and snr vs sample rate, pga = 0, dith = 0, rand = 0 ltc2205: sfdr and snr vs v dd , 30.1mhz input pga = 0, dith = 0, rand = 0 ltc2205: iv dd vs sample rate, pga = 0, dith = 0, rand = 0 typical perfor a ce characteristics uw
ltc2205/ltc2204 12 22054p typical perfor a ce characteristics uw ltc2204: typical inl ltc2204: typical dnl ltc2204: shorted input ltc2204: 131072 point fft, f in = 5.1mhz, C1db, pga = 0, dith = 0, rand = 0 ltc2204: 131072 point fft, f in = 5.1mhz, C1db, pga = 0, dith = 1, rand = 0 ltc2204: 131072 point fft, f in = 5.1mhz, C1db, pga = 0, dith = 1, rand = 1 ltc2204: 32768 point fft, f in = 25.1mhz, C1db, pga = 0, dith = 0, rand = 0 ltc2204: 32768 point fft, f in = 25.1mhz, C10db, pga = 0, dith = 0, rand = 0 ltc2204: 32768 point fft, f in = 25.1mhz, C20db, pga = 0, dith = 0, rand = 0
ltc2205/ltc2204 13 22054p typical perfor a ce characteristics uw ltc2204: 32768 point fft, f in = 70.1mhz, C1db, pga = 0, dith = 0, rand = 0 ltc2204: 32768 point fft, f in = 70.1mhz, C10db, pga = 0, dith = 0, rand = 0 ltc2204: 32768 point fft, f in = 70.1mhz, C20db, pga = 0, dith = 0, rand = 0 ltc2204: 32768 point fft, f in = 140.1mhz, C1db, pga = 1, dith = 0, rand = 0 ltc2204: 32768 point fft, f in = 140.1mhz, C10db, pga = 1, dith = 0, rand = 0 ltc2204: 32768 point fft, f in = 140.1mhz, C20db, pga = 1, dith = 0, rand = 0 ltc2204: 32768 point fft, f in = 170.1mhz, C1db, pga = 1, dith = 0, rand = 0 ltc2204: 32768 point fft, f in = 170.1mhz, C10db, pga = 1, dith = 0, rand = 0 ltc2204: 32768 point fft, f in = 170.1mhz, C20db, pga = 1, dith = 0, rand = 0
ltc2205/ltc2204 14 22054p typical perfor a ce characteristics uw ltc2204: 32768 point fft, f in = 350.1mhz, C1db, pga = 1, dith = 0, rand = 0 ltc2204: 32768 point fft, f in = 350.1mhz, C10db, pga = 1, dith = 0, rand = 0 ltc2204: 32768 point fft, f in = 350.1mhz, C20db, pga = 1, dith = 0, rand = 0 ltc2204: 32768 point 2-tone fft, f in = 30.1mhz, 31.1mhz, C7db, pga = 0, dith = 0, rand = 0 ltc2204: 32768 point 2-tone fft, f in = 70.1mhz, 71.1mhz, C7db, pga = 0, dith = 0, rand = 0 ltc2204: 32768 point 2-tone fft, f in = 250.1mhz, 251.1mhz, C7db, pga = 1, dith = 0, rand = 0 ltc2204: sfdr vs input level, f in = 5.1mhz, pga = 0, dith = 0, rand = 0 ltc2204: sfdr vs input level, f in = 5.1mhz, pga = 0, dith = 1, rand = 1 ltc2204: sfdr vs input level, f in = 30.1mhz, pga = 0, dith = 0, rand = 0
ltc2205/ltc2204 15 22054p typical perfor a ce characteristics uw ltc2204: sfdr vs input level, f in = 30.1mhz, pga = 0, dith = 1, rand = 1 ltc2204: sfdr vs input level, f in = 70.1mhz, pga = 0, dith = 0, rand = 0 ltc2204: sfdr vs input level, f in = 70.1mhz, pga = 0, dith = 1, rand = 1 ltc2204: sfdr vs input level, f in = 140.1mhz, pga = 0, dith = 0, rand = 0 ltc2204: sfdr vs input level, f in = 140.1mhz, pga = 0, dith = 1, rand = 1 ltc2204: sfdr vs input level, f in = 170.1mhz, pga = 0, dith = 0, rand = 0 ltc2204: sfdr vs input level, f in = 170.1mhz, pga = 0, dith = 1, rand = 1 ltc2204: sfdr vs input level, f in = 350.1mhz, pga = 0, dith = 0, rand = 0 ltc2204: sfdr vs input level, f in = 350.1mhz, pga = 0, dith = 1, rand = 1
ltc2205/ltc2204 16 22054p ltc2204: snr vs input frequency, pga = 0, dith = 0, rand = 0 ltc2204: snr vs input frequency, pga = 1, dith = 0, rand = 0 ltc2204: sfdr (hd2 and hd3) vs input frequency, pga = 0, dith = 0, rand = 0 ltc2204: sfdr (hd2 and hd3) vs input frequency, pga = 1, dith = 0, rand = 0 ltc2204: sfdr (hd4 and higher) vs input frequency, pga = 0, dith = 0, rand = 0 ltc2204: sfdr (hd4 and higher) vs input frequency, pga = 1, dith = 0, rand = 0 ltc2204: sfdr and snr vs sample rate, pga = 0, dith = 0, rand = 0 ltc2204: sfdr and snr vs v dd , 30.1mhz input pga = 0, dith = 0, rand = 0 ltc2204: iv dd vs sample rate, pga = 0, dith = 0, rand = 0 typical perfor a ce characteristics uw
ltc2205/ltc2204 17 22054p sense (pin 1): reference mode select and external reference input. tie sense to v dd to select the internal 2.5v bandgap reference. an external reference of 2.5v or 1.25v may be used; both reference values will set a full scale adc range of 2.25v (pga = 0). v cm (pin 2): 1.25v output. optimum voltage for input com- mon mode. must be bypassed to ground with a minimum of 2.2f. ceramic chip capacitors are recommended. v dd (pins 3, 4, 12, 13, 14): 3.3v analog supply pin. bypass to gnd with 0.1f ceramic chip capacitors. gnd (pins 5, 8, 11, 15, 48, 49): adc power ground. a in + (pin 6): positive differential analog input. a in C (pin 7): negative differential analog input. enc + (pin 9): positive differential encode input. the sampled analog input is held on the rising edge of enc + . internally biased to 1.6v through a 6.2k resistor. enc C (pin 10): negative differential encode input. the sampled analog input is held on the falling edge of enc C . internally biased to 1.6v through a 6.2k resistor. by- pass to ground with a 0.1f capacitor for a single-ended encode signal. shdn (pin 16): power shutdown pin. shdn = low results in normal operation. shdn = high results in powered down analog circuitry and the digital outputs are placed in a high impedance state. dith (pin 17): internal dither enable pin. dith = low disables internal dither. dith = high enables internal dither. refer to internal dither section of this data sheet for details on dither operation. d0-d15 (pins 18-22, 26-28, 32-35 and 39-42): digital outputs. d15 is the msb. ognd (pins 23, 31 and 38): output driver ground. ov dd (pins 24, 25, 36, 37): positive supply for the output drivers. bypass to ground with 0.1f capacitor. clkout C (pin 29): data valid output. clkout C will toggle at the sample rate. latch the data on the falling edge of clkout C . clkout + (pin 30): inverted data valid output. clkout + will toggle at the sample rate. latch the data on the rising edge of clkout + . of (pin 43): over/under flow digital output. of is high when an over or under ? ow has occurred. oe (pin 44): output enable pin. low enables the digital output drivers. high puts digital outputs in hi-z state. mode (pin 45): output format and clock duty cycle stabilizer selection pin. connecting mode to 0v selects straight binary output format and disables the clock duty cycle stabilizer. connecting mode to 1/3v dd selects straight binary output format and enables the clock duty cycle stabilizer. connecting mode to 2/3v dd selects 2s complement output format and enables the clock duty cycle stabilizer. connecting mode to v dd selects 2s complement output format and disables the clock duty cycle stabilizer. rand (pin 46): digital output randomization selection pin. rand low results in normal operation. rand high selects d1-d15 to be exclusive-ored with d0 (the lsb). the output can be decoded by again applying an xor operation between the lsb and all other bits. this mode of operation reduces the effects of digital output interferance. pga (pin 47): programmable gain ampli? er control pin. low selects a front-end gain of 1, input range of 2.25v p-p . high selects a front-end gain of 1.5, input range of 1.5v p-p . gnd (exposed pad, pin 49): adc power ground. the ex- posed pad on the bottom of the package must be soldered to ground. pi fu ctio s uuu
ltc2205/ltc2204 18 22054p block diagra w adc clocks differential input low jitter clock driver dither signal generator first pipelined adc stage fifth pipelined adc stage fourth pipelined adc stage second pipelined adc stage enc + enc ? correction logic and shift register dith m0de ognd clkout+ clkout ? of d15 d14 ov dd d1 d0 22054 f01 input s/h a in ? a in + third pipelined adc stage output drivers control logic pga rand lvds shdn v dd gnd pga sense v cm buffer adc reference voltage reference range select figure 1. functional block diagram
ltc2205/ltc2204 19 22054p dynamic performance signal-to-noise plus distortion ratio the signal-to-noise plus distortion ratio [s/(n+d)] is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the adc output. the output is band lim- ited to frequencies above dc to below half the sampling frequency. signal-to-noise ratio the signal-to-noise (snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components, except the ? rst ? ve harmonics. total harmonic distortion total harmonic distortion is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd = C20log (v 2 2 + v 3 2 + v 4 2 + ... v n 2 )/v 1 2 where v 1 is the rms amplitude of the fundamental fre- quency and v 2 through v n are the amplitudes of the second through nth harmonics. intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies fa and fb are applied to the adc input, nonlinearities in the adc transfer function can create distortion products at the sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. for example, the 3nd order imd terms include (2fa + fb), (fa + 2fb), (2fa - fb) and (fa - 2fb). the 3rd order imd is de? ned as the ration of the rms value of either input tone to the rms value of the largest 3rd order imd product. spurious free dynamic range (sfdr) spurious free dynamic range is difference between the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and dc. this value is expressed in decibel relative to the rms value of a full scale input signal. full power bandwidth the full power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full scale input signal. aperture delay time the time from when a rising enc + equals the enc C voltage to the instant that the input signal is held by the sample- and-hold circuit. aperture delay jitter the variation in the aperture delay time from convertion to conversion. this random variation will result in noise when sampling an ac input. the signal to noise ratio due to the jitter alone will be: snr jitter = C20log (2 ) ? f in ? t jitter operatio u
ltc2205/ltc2204 20 22054p converter operation the ltc2205/ltc2204 are cmos pipelined multistep con- verters with a front-end pga. as shown in figure 1, the con- verter has ? ve pipelined adc stages; a sampled analog input will result in a digitized value seven cycles later (see the timing diagram section). the analog input is differential for improved common mode noise immunity and to maximize the input range. additionally, the differential input drive will reduce even order harmonics of the sample and hold circuit. the encode input is also differential for improved common mode noise immunity. the ltc2205/ltc2204 have two phases of operation, deter- mined by the state of the differential enc + /enc C input pins. for brevity, the text will refer to enc + greater than enc C as enc high and enc + less than enc C as enc low. each pipelined stage shown in figure 1 contains an adc, a reconstruction dac and an interstage ampli? er. in operation, the adc quantizes the input to the stage and the quantized value is subtracted from the input by the dac to produce a residue. the residue is ampli? ed and output by the residue ampli? er. successive stages oper- ate out of phase so that when odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. when enc is low, the analog input is sampled differen- tially directly onto the input sample-and-hold capacitors, inside the input s/h shown in the block diagram. at the instant that enc transitions from low to high, the voltage on the sample capacitors is held. while enc is high, the held input voltage is buffered by the s/h ampli? er which drives the ? rst pipelined adc stage. the ? rst stage acquires the output of the s/h ampli? er during the high phase of enc. when enc goes back low, the ? rst stage produces its residue which is acquired by the second stage. at the same time, the input s/h goes back to acquiring the analog input. when enc goes high, the second stage produces its residue which is acquired by the third stage. an identical process is repeated for the third and fourth stages, resulting in a fourth stage residue that is sent to the ? fth stage for ? nal evaluation. each adc stage following the ? rst has additional range to accommodate ? ash and ampli? er offset errors. results from all of the adc stages are digitally delayed such that the results can be properly combined in the correction logic before being sent to the output buffer. applicatio s i for atio wu u u sample/hold operation and input drive sample/hold operation figure 2 shows an equivalent circuit for the ltc2205/ ltc2204 cmos differential sample and hold. the differ- ential analog inputs are sampled directly onto sampling capacitors (c sample ) through nmos transitors. the capacitors shown attached to each input (c parasitic ) are the summation of all other capacitance associated with each input. during the sample phase when enc is low, the nmos transistors connect the analog inputs to the sampling capacitors and they charge to, and track the differential input voltage. when enc transitions from low to high, the sampled input voltage is held on the sampling capacitors. during the hold phase when enc is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the adc core for processing. as enc transitions for high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. if the change between the last sample and the new sample is small, figure 2. equivalent input circuit c sample 4.9pf v dd v dd ltc2005/ltc2004 a in + 22054 f02 c sample 4.9pf v dd a in ? enc ? enc + 1.6v 6k 1.6v 6k c parasitic 1.8pf c parasitic 1.8pf
ltc2205/ltc2204 21 22054p the charging glitch seen at the input will be small. if the input change is large, such as the change seen with input frequencies near nyquist, then a larger charging glitch will be seen. common mode bias the adc sample-and-hold circuit requires differential drive to achieve speci? ed performance. each input should swing 0.5625v for the 2.25v range (pga = 0) or 0.375v for the 1.5v range (pga = 1), around a common mode voltage of 1.25v. the v cm output pin (pin 3) is designed to provide the common mode bias level. v cm can be tied directly to the center tap of a transformer to set the dc input level or as a reference level to an op amp differential driver circuit. the v cm pin must be bypassed to ground close to the adc with 2.2f or greater. input drive impedence as with all high performance, high speed adcs the dynamic performance of the ltc2205/ltc2204 can be in? uenced by the input drive circuitry, particularly the second and third harmonics. source impedance and in- put reactance can in? uence sfdr. at the falling edge of enc the sample-and-hold circuit will connect the 4.9pf sampling capacitor to the input pin and start the sampling period. the sampling period ends when enc rises, hold- ing the sampled input on the sampling capacitor. ideally, the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2f encode ); however, this is not always possible and the incomplete settling may degrade the sfdr. the sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. for the best performance it is recomended to have a source impedence of 100 or less for each input. the source impedence should be matched for the differential inputs. poor matching will result in higher even order harmonics, especially the second. input drive circuits input filtering a ? rst order rc lowpass ? lter at the input of the adc can serve two functions: limit the noise from input cir- cuitry and provide isolation from adc s/h switching. the ltc2205/ltc2204 have a very broadband s/h circuit, dc to 700mhz; it can be used in a wide range of applications; therefore, it is not possible to provide a single recom- mended rc ? lter. figures 3, 4a and 4b show three examples of input rc ? ltering at three ranges of input frequencies. in general it is desirable to make the capacitors as large as can be toleratedthis will help suppress random noise as well as noise coupled from the digital circuitry. the ltc2205/ ltc2204 do not require any input ? lter to achieve data sheet speci? cations; however, no ? ltering will put more stringent noise requirements on the input drive circuitry. transformer coupled circuits figure 3 shows the ltc2205/ltc2204 being driven by an rf transformer with a center-tapped secondary. the secondary center tap is dc biased with v cm , setting the adc input signal at its optimum dc level. figure 3 shows a 1:1 turns ratio transformer. other turns ratios can be used; however, as the turns ratio increases so does the impedance seen by the adc. source impedance greater than 50 can reduce the input bandwidth and increase high frequency distortion. a disadvantage of using a transformer is the loss of low frequency response. most small rf transformers have poor performance at frequen- cies below 1mhz. center-tapped transformers provide a convenient means of dc biasing the secondary; however, they often show poor balance at high input frequencies, resulting in large 2nd order harmonics. figure 3. single-ended to differential conversion using a transformer. recommended for input frequencies from 5mhz to 50mhz applicatio s i for atio wu u u 25 ? 25 ? 10 ? 10 ? 0.1 f a in + a in ? 12pf 2.2 f 12pf 12pf v cm ltc2205/ ltc2204 analog input 0.1 ft1 1:1 t1 = ma/com etc1-1t resistors, capacitors are 0402 package size except 2.2 f 22054 f03
ltc2205/ltc2204 22 22054p figure 4a shows transformer coupling using a transmis- sion line balun transformer. this type of transformer has much better high frequency response and balance than ? ux coupled center tap transformers. coupling capacitors are added at the ground and input primary terminals to allow the secondary terminals to be biased at 1.25v. figure 4b shows the same circuit with components suitable for higher input frequencies. figure 5. dc coupled input with differential ampli? er 0.1 f a in + a in ? 4.7pf 2.2 f 4.7pf 4.7pf v cm ltc2205/ ltc2204 analog input 0.1 f 0.1 f t1 1:1 t1 = ma/com etc1-1-13 resistors, capacitors are 0402 package size except 2.2 f 22054 f04a 25 ? 10 ? 200 ? 200 ? 10 ? 25 ? figure 4a. using a transmission line balun transformer. recommended for input frequencies from 50mhz to 250mhz 0.1 f a in + a in ? 2.2 f 2.2pf 2.2pf v cm ltc2205/ ltc2204 analog input 0.1 f 0.1 f t1 1:1 t1 = ma/com etc1-1-13 resistors, capacitors are 0402 package size except 2.2 f 22054 f04b 25 ? 200 ? 200 ? 25 ? figure 4b. using a transmission line balun transformer. recommended for input frequencies from 250mhz to 500mhz ? ? + + a in + a in ? 2.2 f 12pf 12pf v cm ltc2205/ ltc2204 analog input 22054 f05 cm amplifier = ltc6600-20, ltc1993, etc. high speed differential amplifier 25 ? 25 ? high noise. as a result, the snr will be degraded unless the noise bandwidth is limited prior to the adc input. pga 1.25v sense v cm buffer internal adc reference range select and gain control 2.5v bandgap reference 2.2 f tie to v dd to use internal 2.5v reference or input for external 2.5v reference or input for external 1.25v reference 22054 f06 ltc2205/ ltc2204 figure 6. reference circuit applicatio s i for atio wu u u reference operation figure 6 shows the ltc2205/ltc2204 reference circuitry consisting of a 2.5v bandgap reference, a programmable gain ampli? er and control circuit. the ltc2205/ltc2204 have three modes of reference operation: internal refer- ence, 1.25v external reference or 2.5v external reference. to use the internal reference, tie the sense pin to v dd . to use an external reference, simply apply either a 1.25v or 2.5v reference voltage to the sense input pin. both 1.25v and 2.5v applied to sense will result in a full scale range of 2.25v p-p (pga = 0). a 1.25v output, v cm is provided for a common mode bias for input drive circuitry. an external bypass capacitor is required for the v cm output. this provides a high frequency low impedance path to direct coupled circuits figure 5 demonstrates the use of a differential ampli? er to convert a single ended input signal into a differential input signal. the advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of any op amp or closed-loop ampli? er will de- grade the adc sfdr at high input frequencies. additionally, wideband op amps or differential ampli? ers tend to have
ltc2205/ltc2204 23 22054p ground for internal and external circuitry. this is also the compensation capacitor for the reference; it will not be stable without this capacitor. the minimum value required for stability is 2.2f. the internal programmable gain ampli? er provides the internal reference voltage for the adc. this ampli? er has very stringent settling requirements and is not accessible for external use. the sense pin can be driven 5% around the nominal 2.5v or 1.25v external reference inputs. this adjustment range can be used to trim the adc gain error or other system gain errors. when selecting the internal reference, the sense pin should be tied to v dd as close to the converter as possible. if the sense pin is driven externally it should be bypassed to ground as close to the device as possible with 1f (or larger) ceramic capacitor. figure 7. a 2.25v range adc with an external 2.5v reference v cm sense 1.25v 3.3v 2.2 f 2.2 f 1 f 22054 f07 ltc2205/ ltc2204 ltc1461-2.5 2 6 4 applicatio s i for atio wu u u differentially, primarily for noise immunity from common mode noise sources. each input is biased through a 6k resistor to a 1.6v bias. the bias resistors set the dc oper- ating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. any noise present on the encode signal will result in ad- ditional aperture jitter that will be rms summed with the inherent adc aperture jitter. in applications where jitter is critical (high input frequen- cies), take the following into consideration: 1. differential drive should be used. 2. use as large an amplitude possible. if using trans- former coupling, use a higher turns ratio to increase the amplitude. 3. if the adc is clocked with a ? xed frequency sinusoidal signal, ? lter the encode signal to reduce wideband noise. 4. balance the capacitance and series resistance at both encode inputs such that any coupled noise will appear at both inputs as common mode noise. the encode inputs have a common mode range of 1.2v to v dd . each input may be driven from ground to v dd for single-ended drive. pga pin the pga pin selects between two gain settings for the adc front-end. pga = 0 selects an input range of 2.25v p-p ; pga = 1 selects an input range of 1.5v p-p . the 2.25v input range has the best snr; however, the distortion will be higher for input frequencies above 100mhz. for applica- tions with high input frequencies, the low input range will have improved distortion; however, the snr will be 1.8db worse. see the typical performance curves section. driving the encode inputs the noise performance of the ltc2205/ltc2204 can depend on the encode signal quality as much as for the analog input. the encode inputs are intended to be driven figure 8. transformer driven encode v dd v dd ltc2205/ltc2204 22054 f08 v dd enc ? enc + 1.6v 1.6v t1 1:4 0.1 f encode input 6k 6k to internal adc clock drivers
ltc2205/ltc2204 24 22054p the lower limit of the ltc2205/ltc2204 sample rate is determined by droop of the sample and hold circuits. the pipelined architecture of this adc relies on storing analog signals on small valued capacitors. junction leakage will discharge the capacitors. the speci? ed minimum operating frequency for the ltc2205/ltc2204 is 1msps. digital outputs digital output buffers figure 11 shows an equivalent circuit for a single output buffer. each buffer is powered by ov dd and ognd, isolated from the adc power and ground. the additional n-channel transistor in the output driver allows operation down to low voltages. the internal resistor in series with the output eliminates the need for external damping resistors. as with all high speed/high resolution converters, the digi- tal output loading can affect the performance. the digital outputs of the ltc2205/ltc2204 should drive a minimum capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. the output should be buffered with a device such as a alvch16373 cmos latch. for full speed operation the capacitive load should be kept under 10pf. a resistor in series with the output may be used but is not required since the adc has a series resistor of 33 on chip. lower ov dd voltages will also help reduce interference from the digital outputs. 22054 f10 enc ? enc + 3.3v 3.3v d0 q0 q0 mc100lvelt22 ltc2205/ ltc2204 figure 10. enc drive using a cmos to pecl translator maximum and minimum encode rates the maximum encode rate for the ltc2205 is 65msps. the maximum encode rate for the ltc2204 is 40msps. for the adc to operate properly the encode signal should have a 50% (2.5%) duty cycle. achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as pecl or lvds. when using a single-ended encode signal asymmetric rise and fall times can result in duty cycles that are far from 50%. an optional clock duty cycle stabilizer can be used if the input clock does not have a 50% duty cycle. this circuit uses the rising edge of enc pin to sample the analog input. the falling edge of enc is ignored and an internal falling edge is generated by a phase-locked loop. the input clock duty cycle can vary from 30% to 70% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. if the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the pll to lock onto the input clock. to use the clock duty cycle stabilizer, the mode pin must be connected to 1/3v dd or 2/3v dd using external resistors. figure 9. single-ended enc drive, not recommended for low jitter 22054 f09 enc ? 1.6v v threshold = 1.6v enc + 0.1 f ltc2205/ ltc2204 applicatio s i for atio wu u u ltc2205/ltc2204 22054 f11 ov dd v dd v dd 0.1 f typical data output ognd ov dd 0.5v to v dd predriver logic data from latch 33 ? figure 11. equivalent circuit for a digital output buffer
ltc2205/ltc2204 25 22054p the digital output is randomized by applying an exclu- sive-or logic operation between the lsb and all other data output bits. to decode, the reverse operation is applied; that is, an exclusive-or operation is applied between the lsb and all other bits. the lsb, of and clkout output are not affected. the output randomizer function is active when the rand pin is high. applicatio s i for atio wu u u data format the ltc2205/ltc2204 parallel digital output can be selected for offset binary or 2s complement format. the format is selected with the mode pin. this pin has a four level logic input, centered at 0, 1/3v dd , 2/3v dd and v dd . an external resistor divider can be user to set the 1/3v dd and 2/3v dd logic levels. table 1 shows the logic states for the mode pin. table 1. mode pin function clock duty mode output format cycle stabilizer 0(gnd) straight binary off 1/3v dd straight binary on 2/3v dd 2s complement on v dd 2s complement off over? ow bit an over? ow output bit (of) indicates when the converter is over-ranged or under-ranged. a logic high on the of pin indicates an over? ow or under? ow. output clock the adc has a delayed version of the encode input available as a digital output. both a noninverted version, clkout+ and an inverted version clkoutC are provided. the clkout+/clkoutC can be used to synchronize the con- verter data to the digital system. this is necessary when using a sinusoidal encode. data can be latched on the rising edge of clkout+ or the falling edge of clkoutC. clkout+ falls and clkoutC rises as the data outputs are updated. digital output randomizer interference from the adc digital outputs is sometimes unavoidable. interference from the digital outputs may be from capacitive or inductive coupling or coupling through the ground plane. even a tiny coupling factor can result in discernible unwanted tones in the adc output spectrum. by randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized, trading a slight increase in the noise ? oor for a large reduction in unwanted tone amplitude. figure 12. functional equivalent of digital output randomizer clkout of d15/d0 d14/d0 d2/d0 d1/d0 d0 d0 d1 rand = high, scramble enabled d2 d14 d15 of ltc2205/ltc2204 clkout rand 22054 f12 output driver power separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. the power supply for the digital output buffers, ov dd , should be tied to the same power supply as for the logic being driven. ov dd can be powered with any logic voltage up to the v dd of the adc. ognd can be powered with any voltage from ground up to 1v and must be less than ov dd . the logic outputs will swing between ognd and ov dd .
ltc2205/ltc2204 26 22054p internal dither the ltc2205/ltc2204 are 16-bit adcs with very linear transfer functions; however, at low input levels even slight imperfections in the transfer function will result in unwanted tones. small errors in the transfer function are usually a result of adc element mismatches. an optional internal dither mode can be enabled to randomize the input location on the adc transfer curve, resulting in improved sfdr for low signal levels. as shown in figure 14, the output of the sample-and-hold ampli? er is summed with the output of a dither dac. the dither dac is driven by a long sequence pseudo-random number generator; the random number fed to the dither dac is also subtracted from the adc result. if the dither dac is precisely calibrated to the adc, very little of the dither signal will be seen at the output. the dither signal that does leak through will appear as white noise. the dither dac is calibrated to result in less than 0.5db elevation in the noise ? oor of the adc, as compared to the noise ? oor with dither off. figure 13. descrambling a scrambled digital output applicatio s i for atio wu u u d1 d0 d2 d14 d15 ltc2205/ ltc2204 pc board fpga clkout of d15/d0 d14/d0 d2/d0 d1/d0 d0 22054 f13 figure 14. functional equivalent block diagram of internal dither circuit ain + ain ? s/h amp digital summation output drivers multibit deep pseudo-random number generator 16-bit pipelined adc core precision dac analog summation clock/duty cycle control clkout of d15 d0 enc dither enable high = dither on low = dither off dith enc analog input 22054 f14 a ltc2205/ltc2204
ltc2205/ltc2204 27 22054p information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. s i for atio applicatio wu u u connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. the ltc2205/ltc2204 differential inputs should run parallel and close to each other. the input traces should be as short as possible to minimize capacitance and to minimize noise pickup. heat transfer most of the heat generated by the ltc2205/ltc2204 is transferred from the die through the bottom-side exposed pad. for good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the pc board. it is critical that the exposed pad and all ground pins are connected to a ground plane of suf? cient area with as many vias as possible. evaluation boards grounding and bypassing the ltc2205/ltc2204 require a printed circuit board with a clean unbroken ground plane; a multilayer board with an internal ground plane is recommended. the pinout of the ltc2205/ltc2204 has been optimized for a ? owthrough layout so that the interaction between inputs and digital outputs is minimized. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. high quality ceramic bypass capacitors should be used at the v dd, v cm , and ov dd pins. bypass capacitors must be located as close to the pins as possible. the traces
ltc2205/ltc2204 28 22054p linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2005 lt 1205 500 ? printed in usa package descriptio u uk package 48-lead plastic qfn (7mm 7mm) (reference ltc dwg # 05-08-1704) 7.00 0.10 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation (wkkd-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (see note 6) pin 1 chamfer 0.40 0.10 48 47 1 2 bottom view?exposed pad 5.15 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uk48) qfn 1103 recommended solder pad pitch and dimensions 0.70 0.05 5.15 0.05 (4 sides) 6.10 0.05 7.50 0.05 0.25 0.05 0.50 bsc package outline related parts part number description comments

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